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HI2325
TM
Data Sheet
March 2000
File Number
4823.1
3.3V Dual 8-Bit, 40MSPS A/D Converter with Internal Reference and Digital Clamp
The HI2325 is a monolithic, dual 8-bit, 40MSPS analog-todigital converter fabricated in an advanced CMOS process. It is designed for high speed applications where integration, bandwidth and accuracy are essential. The HI2325 features a 2-stage parallel architecture. Only one external clock is necessary to drive both converters and an internal voltage reference is provided allowing the system designer to realize an increased level of system integration resulting in decreased cost and power dissipation. The HI2325 has excellent dynamic performance while consuming less than 100mW power at 40MSPS. The A/D only requires a single +3.3V power supply and encode clock. Data output latches are provided which present valid data to the output bus with a latency of 2 clock cycles.
Features
* Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . .40MSPS * 6.5 Bits at fIN = 1MHz * Low Power at 40MSPS. . . . . . . . . . . . . . . . . . . . . 100mW * Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 8mW * Wide Full Power Input Bandwidth. . . . . . . . . . . . . 250MHz * Excellent Channel-to-Channel Isolation . . . . . . . . . >75dB * Internal Digital Clamp * Internal Voltage Reference * Single Supply Voltage Operation . . . . . . . . . . . . . . . +3.3V * TTL/CMOS Compatible Digital Inputs * CMOS Compatible Digital Outputs . . . . . . . . . . . . . . . 3.3V * Offset Binary or 2's Complement Output Format * Dual 8-Bit A/D Converters on a Monolithic Chip
Ordering Information
PART NUMBER HI2325IN TEMP. RANGE (oC) -20 to 85 PACKAGE 48 Ld MQFP/PQFP PKG. NO. Q48.7x7-S
Applications
* Wireless Local Loop * PSK and QAM I&Q Demodulators
Pinout
48 LEAD LQFP TOP VIEW
DVSS CLK AVDD ARBS ARB CLE SEL CLP STB
* Medical Imaging and Instrumentation * Portable Communications * Power Metering * Hand-Held Data Collection Instruments
A2 A1
A3 A4 A5 A6 A7 DVDD DVDD B0 B1 B2 B3 B4
1 2 3 4 5 6 7 8 9 10
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
A0
AVSS AIO AIN AVDD ART ARTS BRTS BRT AVDD BIN BIO AVSS
11 25 12 13 14 15 16 17 18 19 20 21 22 23 24
B7 DVSS
REF1 REF2
REF0
TEST AVSS
2S/B
BRBS
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright (c) Intersil Corporation 2000
BRB
B5
B6
HI2325 Functional Block Diagram
AVDD ARTS BRITS AVSS AVDD ART BRT AIO AIN BIN BIO AVSS
36 35 34 33 32 31 30 29 28 27 26 25
ARB 37 ARBS 38 AVDD 39 STB 40 SEL 41 CLE 42 CLP 43 CLK 44 DVSS 45 A0 46 A1 47 A2 48 CLAMP AND LATCH AND TEST 8 9 8 9 A-CH 8-BIT ADC AND CLAMP DAC B-CH 8-BIT ADC AND CLAMP DAC
24 BRB 23 BRBS 22 AVSS 21 TEST 20 REF2 19 REF1 18 REF0 17 2S/B 16 DVSS 15 B7 14 B6 13 B5
1 A3
2 A4
3 A5
4 A6
5 A7
6 DVDD
7 DVDD
8 B0
9 B1
10 11 12 B2 B3 B4
2
HI2325 Pin Descriptions
PIN NO. 46, 47, 48, 1- 5 8 - 15 6, 7 16 17 SYMBOL A0 - A7 B0 - B7 DVDD DVSS 2S/B I Pull-down resistors are incorporated. Pull-down resistors are incorporated. Pull-down resistors are incorporated. I/O O O EQUIVALENT CIRCUIT DESCRIPTION Digital Output. A0(LSB) - A7(MSB) Digital Output. B0(LSB) - B7(MSB) Digital power supply. Digital ground. Selects output code. H: 2's Compliment Code L: Binary Code Determines the clamp circuit reference data. See the table "Digital Clamp Reference Level". Normally open.
18, 19, 20
REF0 ~ 2
I
21
TEST
I
22, 25 22, 25, 36 23 38 24 37 29 32 30 31 26 35 27 34 28, 33, 39 40
DVSS AVSS BRBS ARBS BRB ARB BRT ART BRTS ARTS BIO AIO BIN AIN AVDD STB I Pull-down resistors are incorporated. Pull-down resistors are incorporated. Pull-down resistors are incorporated. Pull-down resistors are incorporated. Pull-down resistors are incorporated. O
Digital ground. Analog ground. Shorting these pins to AVSS generates voltage of about 0.5V at the BRB and ARB pins. Reference voltage (bottom).
Reference voltage (top).
Shorting these pins to AVDD generates voltage of about 2.5V at the BRT and ART pins. Analog output. The digital clamp circuit comprises a D/A converter whose outputs are available on these pins. Analog input.
I
Analog power supply. Stand-by input. H: Stand-by mode L: Operation mode. Controls the CLP signal polarity. H: CLP is High active L: CLP is Low active. Clamp enable input. H: Enable L: Disable. Clamp pulse input. The polarity can be set to either High or Low by setting SEL. Clock input.
41
SEL
I
42
CLE
I
43
CLP
I
44
CLK
I
3
HI2325
Absolute Maximum Ratings
TA = 25oC
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) 48 Ld MQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (Lead Tips Only)
Supply Voltage, AVCC or DVCC to AGND or DGND . . . . . . . . . . .4V DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to DVCC Analog I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to AVCC
Operating Conditions
Temperature Range HI2325IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER ACCURACY Resolution Integral Linearity Error, INL Differential Linearity Error, DNL (Guaranteed No Missing Codes) Offset Error, VOS Full Scale Error, FSE DYNAMIC CHARACTERISTICS Minimum Conversion Rate Maximum Conversion Rate Effective Number of Bits, ENOB
AVDD = DVDD = +3.3V; VIN = 1.50V; fS = 40MSPS at 50% Duty Cycle; CL = 10pF; TA = 25oC; Unless Otherwise Specified TEST CONDITIONS MIN TYP MAX UNITS
8 fIN = 1MHz fIN = 1MHz fIN = DC fIN = DC -50 -
0.2 0.7 1
50 -
Bits LSB LSB mV LSB
No Missing Codes No Missing Codes fIN = 1MHz fIN = 1MHz
1 40 -
6.5 41
-
MSPS MSPS Bits dB
Signal to Noise and Distortion Ratio, SINAD RMS Signal = ------------------------------------------------------------RMS Noise + Distortion Signal to Noise Ratio, SNR RMS Signal = -----------------------------RMS Noise Total Harmonic Distortion, THD 2nd Harmonic Distortion 3rd Harmonic Distortion Spurious Free Dynamic Range, SFDR Intermodulation Distortion, IMD I/Q Channel Crosstalk I/Q Channel Offset Match I/Q Channel Full Scale Error Match Transient Response Over-Voltage Recovery ANALOG INPUT Maximum Peak-to-Peak Single-Ended Analog Input Range Analog Input Resistance, RINA or RINB Analog Input Capacitance, CINA or CINB
fIN = 1MHz
-
42.5
-
dB
fIN = 1MHz fIN = 1MHz fIN = 1MHz fIN = 1MHz f1 = 1MHz, f2 = 1.02MHz
-
-46 -48 -52 48.5 -75 1.0 0.25 1 1
-
dBc dBc dBc dBc dBc dBc LSB LSB Cycle Cycle
(Note 2) 0.2V Overdrive (Note 2)
-
VINA, VINB = VREF, DC VINA, VINB = 1.5V, DC -
1.0 -
-
V M pF
4
HI2325
Electrical Specifications
PARAMETER Analog Input Bias Current, IBA or IBB Full Power Input Bandwidth, FPBW REFERENCE VOLTAGE INPUT Reference Voltage Input Range Total Reference Resistance, RRIN Reference Current, IRIN Self Bias VRB VRT SAMPLING CLOCK INPUT Input Logic High Voltage, VIH Input Logic Low Voltage, VIL Input Logic High Current, IIH Input Logic Low Current, IIL Input Capacitance, CIN DIGITAL OUTPUTS Output Logic High Voltage, VOH Output Logic Low Voltage, VOL Output Logic High Voltage, VOH Output Logic Low Voltage, VOL Output Capacitance, COUT TIMING CHARACTERISTICS Aperture Delay, tAP Aperture Jitter, tAJ Data Output Hold, tH Data Output Delay, tOD Data Latency, t LAT Power-Up Initialization Sample Clock Pulse Width (Low) Sample Clock Pulse Width (High) Sample Clock Duty Cycle Variation POWER SUPPLY CHARACTERISTICS Analog Supply Voltage, AVDD Digital Supply Voltage, DVDD Supply Current, IDD Power Dissipation Offset Error Sensitivity, VOS Gain Error Sensitivity, FSE NOTES: 2. Parameter guaranteed by design or characterization and not production tested. 3. With the clock low and DC input. A VDD or DVDD = 3.3V 5% A VDD or DVDD = 3.3V 5% (Note 2) (Note 2) fS = 40MSPS 3.0 3.0 3.3 3.3 30.3 100 0.125 0.15 3.6 3.6 V V mA mW LSB LSB For a Valid Sample (Note 2) Data Invalid Time (Note 2) (Note 2) (Note 2) 2 11.25 11.25 4 5 10.7 11.7 2 12.5 12.5 5 2 ns psRMS ns ns Cycles Cycles ns ns % IOH = 100A; DVDD = 3.3V IOL = 1.5mA; DVDD = 3.3V IOH = 100A; DVDD = 3.0V IOL = 100A; DVDD = 3.0V V V V V pF CLK CLK CLK, VIH = 3.3V CLK, VIL = 0V CLK 2.0 0.8 V V A A pF 370 5.4 0.54 1.9 V k mA AVDD = DVDD = +3.3V; VIN = 1.50V; fS = 40MSPS at 50% Duty Cycle; CL = 10pF; TA = 25oC; Unless Otherwise Specified (Continued) TEST CONDITIONS VINA/VINB = ART/BRT, ARB/BRB, DC (Notes 2, 3) fS = 40MHz, (Note 2) MIN TYP MAX UNITS A MHz
5
HI2325
TABLE 1. OUTPUT MODE INPUT TEST L L L H STB L L H X 2S/B L H X X A7 B7 A6 B6 A5 B5 A4 B4 OUTPUT A3 B3 A2 B2 A1 B1 A0 B0
Binary Code 2's Compliment Code Hi-Z Test Mode
TABLE 2. DIGITAL OUTPUT The following table shows the relationship between analog input voltage and digital output code. DIGITAL OUTPUT CODE INPUT SIGNAL VOLTAGE VART, VBRT : : : : VARB, VBRB BINARY CODE STEP 255 : 128 127 : 0 MSB 11111111 : 10000000 01111111 : 00000000 TABLE 3. DIGITAL CLAMP REFERENCE LEVEL SETTING REF2 L L L L H H H H REF1 L L H H L L H H REF0 L H L H L H L H MODE 0 1 2 3 4 5 6 7 DECIMAL 1 16 32 128 254 239 223 127 REFERENCE LEVEL BINARY 00000001 00010000 00100000 10000000 11111110 11101111 11011111 01111111 2's COMPLIMENT 10000001 10010000 10100000 00000000 01111110 01101111 01011111 11111111 LSB 2's COMPLIMENT CODE MSB 011111111 : 00000000 11111111 : 10000000 LSB
6
HI2325 Metric Plastic Quad Flatpack Packages (MQFP/PQFP)
D D1
Q48.7x7-S
48 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE INCHES SYMBOL A A1 B D MIN 0.056 0.000 0.006 0.347 0.272 0.347 0.272 0.012 48 0.020 BSC MAX 0.066 0.007 0.010 0.362 0.279 0.362 0.279 0.027 MILLIMETERS MIN 1.40 0.00 0.15 8.80 6.90 8.80 6.90 0.30 48 0.500 BSC MAX 1.70 0.20 0.26 9.20 7.10 9.20 7.10 0.70 NOTES 5 2 3, 4 2 3, 4 6 Rev. 1 4/95 NOTES:
A SEATING PLANE
E
E1
D1 E E1 L e
PIN 1
N e
-H-
1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2. Dimensions D and E to be determined at seating plane -C- . 3. Dimensions D1 and E1 to be determined at datum plane -H- . 4. Dimensions D1 and E1 do not include mold protrusion. 5. Dimension B does not include dambar protrusion. 6. "N" is the number of terminal positions.
0.10 0.004 0.24 M B 0o-10o A1 -C-
L 0.107/0.177 0.004/0.007
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
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